The present invention relates to corrosion sensitive structures for monitoring corrosion of vias and contact plugs in an active die region. More particularly, the present invention relates to corrosion sensitive structures formed in a scribeline region, which is adjacent the active die region, for monitoring corrosion of metal plugs of the active die region.
FIG. 1 shows a partially fabricated integrated circuit (IC) 10 that may undergo corrosion during or after post-etch cleaning processes. Some significant steps involved in forming partially fabricated integrated circuit (IC) 10 of FIG. 1 include blanket depositing a first dielectric layer 12, such as silicon dioxide (SiO.sub.2), atop substrate layer 16. After first dielectric layer 12 is planarized, a masking layer (not shown), which typically includes photoresist, is blanket deposited over first dielectric layer 12 and patterned by conventional photolithography. Next, the unmasked portions of first dielectric layer 12 are etched to form a contact hole that provides an opening to the underlying device elements, e.g., source, drain and gate electrode, in substrate layer 16.
At this point, the partially fabricated IC is drenched in a bath of post-etch cleaning solution, which removes the etch residue present at the side-walls of the contact hole. Post-etch cleaning solutions may include amine based compounds, which are believed to be the active ingredient for cleaning the contact hole. By way of example, a post-etch cleaning solution EKC265.TM. obtained from EKC Technology Inc. of Hayward, Calif. includes hydroxylamine that is believed to be primarily responsible for removing the etch-residue from the contact hole. Other ingredients of EKC265.TM. include 2-(2-Aminoethoxy)Ethanol and Catechol.
After the post-etch cleaning process has concluded, an adhesion layer (not shown to simplify illustration), e.g., a titanium layer, a barrier layer (not shown to simplify illustration), e.g., a titanium nitride layer, and a tungsten layer are blanket deposited on the partially fabricated IC, filling the contact hole. The surface of the partially fabricated IC typically then undergoes chemical-mechanical polishing to form contact plug 14.
A metallization layer 18 is then blanket deposited and patterned over dielectric layer 12 such that metallization layer 18 partially covers contact plug 14. A post-etch cleaning process described above is carried out to remove post-etch residues from the metallization. Next, a second dielectric layer 20 is deposited over the surface of the partially fabricated IC. A via (hereinafter referred to as "via hole" to distinguish from "via plug," explained below) is etched into second dielectric layer 20 by conventional methods, during which the location of via hole typically misregisters and hangs to one side of metallization layer 18. Furthermore, at this location it is well known in the art that the dielectric layer frequently over etches, as shown in FIG. 1, and forms an opening 24 between metallization 18 and second dielectric layer 20 that extends all the way down to contact plug 14.
Those skilled in the art will recognize that depositing metallization layer 18 in a dogbone formation to prevent the formation of opening 24 is undesired because metallization in dogbone formation consumes significantly larger area on the substrate surface and thereby reduces the number of die formed on a semiconductor wafer.
Via hole 22 then undergoes post-etch cleaning using the post-etch cleaning solution, as described above, to remove the etch residue present at the side-walls of the via hole. Next, an adhesion layer, a barrier layer and a tungsten layer may be deposited on the partially fabricated IC surface and undergo chemical-mechanical polishing to form a via plug, which connects one metallization layer to another metalization layer of an IC. Those skilled in the art will recognize that these steps are followed by similar steps, e.g., depositing and patterning additional metallization layers, post-etch cleaning, depositing additional dielectrice layers, until the IC fabrication is completed.
Unfortunately, the above described process suffers from several drawbacks. By way of example, some of the post-etch cleaning solution composition may remain in the contact hole and via hole, gradually corroding the metal plug, i.e. contact or via plug, formed subsequently. The metal plug, therefore, does not effectively connect the device elements to the first metallization layer or connect one metallization layer to another metallization layer, causing catastrophic device failure.
As another example, during post-etch cleaning of the via hole, opening 24 between the metallization layer 18 and dielectric layer 20 provides the post-etch cleaning solution a pathway to migrate or seep into the underlying contact plug. As a result, over a period of time, the metal, e.g., tungsten, aluminum or copper, composition in the contact plug reacts with the post-etch cleaning solution and is gradually depleted and/or corroded, which may also lead to catastrophic device failure.
As yet another example, during post-etch cleaning of the patterned metallization, some of the post-etch cleaning solvent migrates into the underlying plug throb cracks or fissures formed in the metallization layer during deposition, patterning, etc. of the metallization layer. In other instances, the post-etch cleaning solvent collects or is trapped in the fissures and cracks of the metallization layer and reacts with the metallization layer over a period of time to create pathways that ultimately lead the solvent to the underlying plug, where plug corrosion begins.
What is therefore needed is a corrosion sensitive structure or process of monitoring the corrosion of contact and via plugs in ICs, which process effectively simulates the gradual process of corrosion of contact and via plugs.